The present invention relates to an orthogonal transform processor suitably used for an image processing, a speech processing, etc.
For example, in a compressing and coding system for image data, a small-size orthogonal transform processor is required for transforming spatial domain signals into frequency domain signals. An encoder adopts a forward orthogonal transform such as a discrete cosine transform (hereinafter referred to as DCT) and a discrete sine transform (hereinafter referred to as DST). A decoder adopts an inverse orthogonal transform such as an inverse discrete cosine transform (hereinafter referred to as IDCT) and an inverse discrete sine transform (hereinafter referred to as IDST).
U.S. Pat. No. 4,791,598 discloses a two-dimensional DCT processor comprising two one-dimensional DCT circuits and a transposition memory interposed therebetween. Each of the one-dimensional DCT circuits adopts a so-called fast algorithm and a distributed arithmetic (DA) method, and comprises a butterfly operation circuit including plural adders and subtracters, and a distributed arithmetic circuit, disposed at the subsequent level, for obtaining vector inner products by using not a multiplier but a ROM (read only memory). The distributed arithmetic circuit includes plural ROM/accumulators (hereinafter referred to as RACs). Each of the RACs includes a ROM for storing, in a form of a look-up table, partial sums of the vector inner products based on a discrete cosine matrix, and an accumulator for obtaining a vector inner product corresponding to an input vector by adding, with the digits aligned, the partial sums successively retrieved from the ROM with bit slice words using as addresses. In a one-dimensional IDCT circuit, a butterfly operation circuit is disposed at a level subsequent to plural RACs included in a distributed arithmetic circuit.
In general, human visual sense is more insensitive to high frequency components than to low frequency components. Therefore, for the purpose of improvement in compression efficiency in a DVC (digital video cassette) and the like, a low frequency component in the one-dimensional DCT result is multiplied by a large weighting and a high frequency component is multiplied by a small weighting before coding. However, multiplication for such frequency-depending weighting of the one-dimensional DCT result requires an additional multiplier. U.S. Pat. No. 5,117,381 describes a one-dimensional eight-point DCT circuit for limited weighting. In this circuit, a multiplier for executing multiplication of input data by elements of a discrete cosine matrix is used also for giving the weighting.
The one-dimensional DCT circuit disclosed in U.S. Pat. No. 5,117,381 is disadvantageously limited to application to the eight-point DCT and cannot be applied to arbitrary weighting. Also, this one-dimensional DCT circuit has a problem that the circuit scale and power consumption are larger, owing to the usage of the multiplier, than those of the one-dimensional DCT circuit described in U.S. Pat. No. 4,791,598.
Furthermore, in dealing with an input data matrix comprising N.times.N elements in the two-dimensional DCT processor disclosed in U.S. Pat. No. 4,791,598, each of the two one-dimensional DCT circuits executes N-point one-dimensional DCT. In this case, each of the two one-dimensional DCT circuits includes N RACs. Specifically, this two-dimensional DCT processor requires to include 2N RACs in total, which disadvantageously increases the circuit scale and power consumption.